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1

[IEEE Asia and South Pacific Conference on Design Automation, 2006. - Yokohama, Japan (Jan. 24, 2006)] Asia and South Pacific Conference on Design Automation, 2006. - A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers

Chien-Chang Chen,, Wai-Kei Mak,

Year:

2006

Language:

english

File:

PDF, 410 KB

english, 2006

2

I/O placement for FPGAs with multiple I/O standards

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2004

Language:

english

File:

PDF, 293 KB

english, 2004

3

[IEEE 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013) - Yokohama (2013.1.22-2013.1.25)] 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) - A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules

Fong-Yuan Chang,, Ren-Song Tsay,, Wai-Kei Mak,, Sheng-Hsiung Chen,

Year:

2013

Language:

english

File:

PDF, 441 KB

english, 2013

4

[IEEE 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) - Singapore (2014.01.20-2014.01.23)] 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) - A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules

Wu, Sheng-Kai, Hsu, Po-Yi, Mak, Wai-Kei

Year:

2014

Language:

english

File:

PDF, 290 KB

english, 2014

5

Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design

Lei, Seong-I, Mak, Wai-Kei

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2013

Language:

english

File:

PDF, 1.32 MB

english, 2013

6

MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules

Chang, Fong-Yuan, Tsay, Ren-Song, Mak, Wai-Kei, Chen, Sheng-Hsiung

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2013

Language:

english

File:

PDF, 21.13 MB

english, 2013

7

[ACM Press the 2006 conference - Yokohama, Japan (2006.01.24-2006.01.27)] Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06 - A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers

Chen, Chien-Chang, Mak, Wai-Kei

Year:

2006

Language:

english

File:

PDF, 296 KB

english, 2006

8

[ACM Press the 2018 International Symposium - Monterey, California, USA (2018.03.25-2018.03.28)] Proceedings of the 2018 International Symposium on Physical Design - ISPD '18 - Pin Assignment Optimization for Multi-2.5D FPGA-based Systems

Kuo, Wan-Sin, Zhang, Shi-Han, Mak, Wai-Kei, Sun, Richard, Leow, Yoon Kah

Year:

2018

Language:

english

File:

PDF, 1.14 MB

english, 2018

9

Monte Carlo bounding techniques for determining solution quality in stochastic programs

Wai-Kei Mak, David P. Morton, R.Kevin Wood

Journal:

Operations Research Letters

Year:

1999

Language:

english

File:

PDF, 120 KB

english, 1999

10

A fast hypergraph min-cut algorithm for circuit partitioning

Wai-Kei Mak, D.F. Wong

Journal:

Integration, the VLSI Journal

Year:

2000

Language:

english

File:

PDF, 215 KB

english, 2000

11

Guest Editorial: Field Programmable Technology

George A. Constantinides, Wai-Kei Mak, Theerayod Wiangtong

Journal:

Journal of Signal Processing Systems

Year:

2008

Language:

english

File:

PDF, 89 KB

english, 2008

12

SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement

Yan, J.Z., Chu, C., Wai-Kei Mak

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2011

Language:

english

File:

PDF, 470 KB

english, 2011

13

Power-Driven Flip-Flop Merging and Relocation

Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2012

Language:

english

File:

PDF, 772 KB

english, 2012

14

FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction

Ajwani, G., Chu, C., Wai-Kei Mak

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2011

Language:

english

File:

PDF, 1.38 MB

english, 2011

15

ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules

Yu-Yi Liang, Tien-Yu Kuo, Shao-Huan Wang, Wai-Kei Mak

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2012

Language:

english

File:

PDF, 106 KB

english, 2012

16

Temporal logic replication for dynamically reconfigurable FPGA partitioning

Wai-Kei Mak, Young, E.F.Y.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2003

Language:

english

File:

PDF, 517 KB

english, 2003

17

On optimal board-level routing for FPGA-based logic emulation

Wai-Kei Mak, Wong, D.F.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1997

Language:

english

File:

PDF, 260 KB

english, 1997

18

Minimum replication min-cut partitioning

Wai-Kei Mak, Wong, D.F.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1997

Language:

english

File:

PDF, 229 KB

english, 1997

19

Min-cut partitioning with functional replication for technology-mapped circuits using minimum area overhead

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2002

Language:

english

File:

PDF, 319 KB

english, 2002

20

Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement

Li, Cha-Ru, Mak, Wai-Kei, Wang, Ting-Chi

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2013

Language:

english

File:

PDF, 1.05 MB

english, 2013

21

[IEEE Conference of Asia and South Pacific Design Automation 2003 - Kitakyushu, Japan (21-24 Jan. 2003)] Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003. - Efficient LUT-based FPGA technology mapping for power minimization

Hao Li,, Wai-Kei Mak,, Katkoori, S.

Year:

2003

Language:

english

File:

PDF, 555 KB

english, 2003

22

[IEEE Comput. Soc IEEE Computer Society Annual Symposium on VLSI - Lafayette, LA, USA (19-20 Feb. 2004)] IEEE Computer Society Annual Symposium on VLSI - Force-directed performance-driven placement algorithm for FPGAs

Hao Li,, Wai-Kei Mak,, Katkoori, S.

Year:

2004

File:

PDF, 640 KB

2004

23

[IEEE 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsinchu, Taiwan (2008.04.23-2008.04.25)] 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Power and density-aware buffer insertion

Yi-Ju Ho,, Wai-Kei Mak,

Year:

2008

Language:

english

File:

PDF, 323 KB

english, 2008

24

[IEEE 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) - Singapore (2014.01.20-2014.01.23)] 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) - Flexible packed stencil design with multiple shaping apertures for e-beam lithography

Chu, Chris, Mak, Wai-Kei

Year:

2014

Language:

english

File:

PDF, 374 KB

english, 2014

25

[IEEE Computer Society IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems - Orlando, FL, USA (19-20 April 2001)] Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems - LUT-based FPGA technology mapping for power minimization with optimal depth

Hao Li,, Wai-Kei Mak,, Katkoori, S.

Year:

2001

Language:

english

File:

PDF, 519 KB

english, 2001

26

Pad Assignment for Die-Stacking System-in-Package Design

Wai-Kei Mak,, Yu-Chen Lin,, Chu, C., Ting-Chi Wang,

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2012

Language:

english

File:

PDF, 6.75 MB

english, 2012

27

[IEEE 2007 International Conference on Field-Programmable Technology - Kitakyusyu, Japan (2007.12.12-2007.12.14)] 2007 International Conference on Field-Programmable Technology - Optimal Buffering of FPGA Interconnect for Expected Delay Optimization

He, Yi-Ru, Mak, Wai-Kei

Year:

2007

Language:

english

File:

PDF, 1.31 MB

english, 2007

28

[IEEE Comput. Soc International Conference on Computer Design VLSI in Computers and Processors - Austin, TX, USA (12-15 Oct. 1997)] Proceedings International Conference on Computer Design VLSI in Computers and Processors - Channel segmentation design for symmetrical FPGAs

Wai-Kei Mak,, Wong, D.F.

Year:

1997

Language:

english

File:

PDF, 702 KB

english, 1997

29

[IEEE ISCAS'99. 1999 IEEE International Symposium on Circuits and Systems. VLSI - Orlando, FL, USA (30 May-2 June 1999)] ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349) - A fast hypergraph minimum cut algorithm

Wai-Kei Mak,, Wong, D.F.

Year:

1999

Language:

english

File:

PDF, 440 KB

english, 1999

30

[IEEE 2011 16th Asia and South Pacific Design Automation Conference ASP-DAC 2011 - Yokohama, Japan (2011.01.25-2011.01.28)] 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) - Cut-demand based routing resource allocation and consolidation for routability enhancement

Chang, Fong-Yuan, Chen, Sheng-Hsiung, Tsay, Ren-Song, Mak, Wai-Kei

Year:

2011

Language:

english

File:

PDF, 385 KB

english, 2011

31

[IEEE 2009 Asia and South Pacific Design Automation Conference (ASP-DAC) - Yokohama, Japan (2009.01.19-2009.01.22)] 2009 Asia and South Pacific Design Automation Conference - Signal skew aware floorplanning and bumper signal assignment technique for flip-chip

Cheng-Yu Wang,, Mak, Wai-Kei

Year:

2009

Language:

english

File:

PDF, 617 KB

english, 2009

32

E-Beam Lithography Character and Stencil Co-Optimization

Wai-Kei Mak,, Chu, Chris

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2014

Language:

english

File:

PDF, 7.65 MB

english, 2014

33

[IEEE Comput. Soc. Press IEEE International Conference on Computer Aided Design (ICCAD) - San Jose, CA, USA (5-9 Nov. 1995)] Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) - Board-level multi-terminal net routing for FPGA-based logic emulation

Wai-Kei Mak,, Wong, D.F.

Year:

1995

Language:

english

File:

PDF, 594 KB

english, 1995

34

[IEEE 2014 15th International Symposium on Quality Electronic Design (ISQED) - Santa Clara, CA, USA (2014.03.3-2014.03.5)] Fifteenth International Symposium on Quality Electronic Design - Double patterning-aware detailed routing with mask usage balancing

Lei, Seong-I, Chu, Chris, Mak, Wai-Kei

Year:

2014

Language:

english

File:

PDF, 197 KB

english, 2014

35

[IEEE 2007 Asia and South Pacific Design Automation Conference - Yokohama, Japan (2007.01.23-2007.01.26)] 2007 Asia and South Pacific Design Automation Conference - Voltage Island Generation under Performance Requirement for SoC Designs

Mak, Wai-Kei, Chen, Jr-Wei

Year:

2007

Language:

english

File:

PDF, 338 KB

english, 2007

36

[ACM 32nd Design Automation Conference - San Francisco, CA (1995.6.12-1995.6.12)] 32nd Design Automation Conference - On Optimal Board-Level Routing for FPGA-based Logic Emulation

Year:

2006

Language:

english

File:

PDF, 193 KB

english, 2006

37

[IEEE 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT) - Hsinchu, Taiwan (27-29 April 2005)] 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). - Faster min-cut computation in unweighted hypergraphs/circuit netlists

Year:

2005

Language:

english

File:

PDF, 666 KB

english, 2005

38

[IEEE Comput. Soc. Press International Conference on Computer Aided Design - San Jose, CA, USA (10-14 Nov. 1996)] Proceedings of International Conference on Computer Aided Design - Minimum replication min-cut partitioning

Wai-Kei Mak,, Wong, D.F.

Year:

1996

Language:

english

File:

PDF, 560 KB

english, 1996

39

[IEEE 2009 10th International Symposium on Quality of Electronic Design (ISQED) - San Jose, CA, USA (2009.03.16-2009.03.18)] 2009 10th International Symposium on Quality of Electronic Design - Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution

Chun-Yu Chuang,, Wai-Kei Mak,

Year:

2009

Language:

english

File:

PDF, 2.46 MB

english, 2009

40

[IEEE ASP-DAC 2005. Asia and South Pacific Design Automation Conference 2005 - Shanghai, China (18-21 Jan. 2005)] Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. - Modern FPGA constrained placement

Year:

2005

Language:

english

File:

PDF, 1.02 MB

english, 2005

41

[IEEE 2007 International Symposium on VLSI Design, Automation and Test - Hsinchu, Taiwan (2007.04.25-2007.04.27)] 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - /spl lambda/-Geometry Clock Tree Construction with Wirelength and Via Minimization

Wang, Chun-Hao, Mak, Wai-Kei

Year:

2007

Language:

english

File:

PDF, 3.81 MB

english, 2007

42

[IEEE 2011 International Conference on Field Programmable Logic and Applications (FPL) - Chania, Greece (2011.09.5-2011.09.7)] 2011 21st International Conference on Field Programmable Logic and Applications - Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign

Lei, Seong-I, Mak, Wai-Kei

Year:

2011

Language:

english

File:

PDF, 513 KB

english, 2011

43

[IEEE Conference, Emerging Information Technology 2005. - NTU, Taipei, Taiwan (Aug. 15-16, 2005)] Conference, Emerging Information Technology 2005. - Placement for modern FPGAs

Wai-Kei Mak,, Hao Li,

Year:

2005

Language:

english

File:

PDF, 138 KB

english, 2005

44

Carriage niches and molecular epidemiology of Staphylococcus lugdunensis and methicillin-resistant S. lugdunensis among patients undergoing long-term renal replacement therapy

Ho, Pak-Leung, Leung, Sammy Man-Him, Chow, Kin-Hung, Tse, Cindy Wing-Sze, Cheng, Vincent Chi-Chung, Tse, Herman, Mak, Siu-Ka, Lo, Wai-Kei

Journal:

Diagnostic Microbiology and Infectious Disease

Year:

2015

Language:

english

File:

PDF, 224 KB

english, 2015

45

Low-power gated and buffered clock network construction

Chao, Wei-Chung, Mak, Wai-Kei

Journal:

ACM Transactions on Design Automation of Electronic Systems

Year:

2008

Language:

english

File:

PDF, 715 KB

english, 2008

46

Power minimization algorithms for LUT-based FPGA technology mapping

Li, Hao, Katkoori, Srinivas, Mak, Wai-Kei

Journal:

ACM Transactions on Design Automation of Electronic Systems

Year:

2004

Language:

english

File:

PDF, 138 KB

english, 2004

47

Board-level multiterminal net routing for FPGA-based logic emulation

Mak, Wai-Kei, Wong, D. F.

Journal:

ACM Transactions on Design Automation of Electronic Systems

Year:

1997

Language:

english

File:

PDF, 367 KB

english, 1997

48

[ACM Press the The 51st Annual Design Automation Conference - San Francisco, CA, USA (2014.06.01-2014.06.05)] Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14 - Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout

Ding, Yixiao, Chu, Chris, Mak, Wai-Kei

Year:

2014

Language:

english

File:

PDF, 143 KB

english, 2014

49

[ACM Press the 11th Great Lakes Symposium - West Lafayette, Indiana, United States (2001..-..)] Proceedings of the 11th Great Lakes Symposium on VLSI - GLSVLSI '01 - Faster and more accurate wiring evaluation in interconnect-centric floorplanning

Chen, Hung-Ming, Wong, D. F., Mak, Wai-Kei, Yang, Hannah H.

Year:

2001

File:

PDF, 173 KB

2001

50

[ACM Press the 2001 international symposium - Sonoma, California, United States (2001.04.01-2001.04.04)] Proceedings of the 2001 international symposium on Physical design - ISPD '01 - Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead

Year:

2001

Language:

english

File:

PDF, 198 KB

english, 2001